1. Field of the Invention
The present invention relates to power supply systems and methods and, more particularly, to an all digital power supply system and method that provides a substantially constant supply voltage over changes in PVT without a band gap reference voltage.
2. Description of the Related Art
A DC-to-DC switching converter is a device that converts one DC voltage to another DC voltage with very little power loss. A boost converter is one type of DC-to-DC switching converter that receives an input voltage of one polarity, and outputs a voltage of the same polarity that is larger than the input voltage. A buck converter is another type of DC-to-DC switching converter that receives an input voltage of one polarity, and outputs a voltage of the same polarity that is smaller than the input voltage.
FIG. 1A shows a block diagram that illustrates a conventional buck converter 100. As shown in FIG. 1A, converter 100 has a power supply circuit 102 that receives a pulse width modulated signal PWS, and generates a supply voltage VDD in response to the pulse width modulated signal PWS.
Power supply circuit 102 includes a DC voltage source 110 and an n-channel MOS transistor 112 that has a source, a drain connected to voltage source 110, and a gate connected to receive the pulse width modulated signal PWS. Circuit 102 also includes a diode D that has an input connected to ground, and an output connected to the source of transistor 112.
In addition, power supply circuit 102 includes an inductor L and a capacitor C that form a LC network. Inductor L has a first end connected to the source of transistor 112, and a second end connected to a supply node NS, while capacitor C has a first end connected to the supply node NS, and a second end connected to ground. Further, a load 114 is connected between the supply node NS and ground.
In operation, the pulse width modulated signal PWS turns transistor 112 on and off, which outputs a pulsed current to the LC network. The LC network averages the pulsed current to generate the supply voltage VDD on the supply node NS. The supply voltage VDD has a value approximately equal to the duty cycle of the pulse width modulated signal PWS multiplied times the voltage of voltage source 110. For example, when a 50% duty cycle signal is used with a 2V-voltage source, a supply voltage VDD of approximately 1V results.
Diode D is used to provide a continuous conductive path for inductor L. When transistor 112 turns on, current is driven into inductor L, which stores the energy. When transistor 112 turns off, the stored energy is transferred to capacitor C as the voltage on the input of inductor L drops below ground. When the voltage on the input of inductor L drops below ground, diode D turns on, thereby providing a continuous conductive path.
Referring again to FIG. 1A, converter 100 also has a compensation circuit 116 that adjusts the duty cycle of the pulse width modulated signal PWS to maintain a roughly constant supply voltage VDD in response to changes in process, voltage, and temperature (PVT).
As shown, compensation circuit 116 includes an adjuster block 120 that divides down (or gains up) the supply voltage VDD on the supply node NS to output an adjusted voltage VA. In addition, circuit 116 includes an error block 122 that compares the adjusted voltage VA to a band gap reference voltage VBG to generate an error voltage VER.
Compensation circuit 116 further includes a proportional integrator differentiator (PID) 124 that responds to changes in the error voltage VER, and outputs a control voltage VC in response thereto, and a pulse width modulator 126 that outputs the pulse width modulated signal PWS.
The LC network is a two pole resonant system that stores energy. As a result, any transient introduced to the system, such as a start up transient or a load transient, causes a disturbance. The disturbance causes a response through the LC network that produces an oscillation or a ringing effect.
PID 124 eliminates the ringing effect by providing a zero that cancels one of the poles in the LC network. Canceling one of the poles, in turn, results in a first order system that is inherently stable. Thus, PID 124 converts the second order response of the LC network to a first order response.
Pulse width modulator 126 varies the positive widths (duty cycles) of the pulses in the pulse width modulated signal PWS in response to the control voltage VC output by PID 124. For example, a centered control voltage produces a pulse width modulated signal PWS with a 50% duty cycle. In addition, a driver block 128 drives the pulse width modulated signal PWS onto the gate of transistor 112.
In operation, the band gap reference voltage VBG is generated by a band gap circuit, and is roughly constant over changes in process, voltage, and temperature (PVT). Under normal operating conditions, the adjusted voltage VA and the band gap reference voltage VBG are equal and the error voltage VER is zero. A zero error voltage produces a control voltage VC which, in turn, produces a pulse width modulated signal PWS.
When the adjusted voltage VA varies due to changes in PVT, error block 122 outputs the error voltage VER with a non-zero value. PID 124 filters the error voltage VER to output a control voltage VC. Pulse width modulator 126 responds to the control voltage VC by varying the duty cycle of the pulse width modulated signal PWS which, in turn, changes the supply voltage VDD. This process continues until the adjusted voltage VA and the band gap reference voltage VBG are again equal.
Thus, compensation circuit 116 adjusts the duty cycle of the pulse width modulated signal PWS to maintain a roughly constant supply voltage VDD in response to changes in process, voltage, and temperature (PVT).
One drawback of switching converter 100 is that diode D introduces an undesirable resistance. One approach to reducing the resistance introduced by diode D is to use a synchronous rectifier. FIG. 1B shows a block diagram that illustrates a conventional synchronous rectifier 150.
As shown in FIG. 1B, synchronous rectifier 150 includes a PMOS driver transistor 152 that has a source connected to a supply voltage VDD, a drain connected to inductor L, and a gate. Rectifier 150 also has a NMOS driver transistor 154 that has a source connected to ground, a drain connected to an inductor node NL, and a gate.
As further shown in FIG. 1B, synchronous rectifier 150 also has a gate signal generator 156 that receives a pulse width modulated signal PWS, and outputs non-overlapping gate signals G1 and G2 to PMOS transistor 152 and NMOS transistor 154, respectively.
In operation, when the pulse width modulated signal PWS transitions low, generator 156 turns off NMOS transistor 154 via gate signal G2, and then turns on PMOS transistor 152 via gate signal G1. When PMOS transistor 152 turns on, transistor 152 sources current into inductor node NL.
When the pulse width modulated signal PWS transitions high, generator 156 turns off PMOS transistor 152 via gate signal G1, and then turns on NMOS transistor 154 via gate signal G2. When NMOS transistor 154 turns on, transistor 154 provides a path to ground to provide a continuous conductive path at the inductor node NL for an inductor.
Another drawback of switching converter 100 is that the converter requires a band gap reference voltage source to respond to changes in PVT. A band gap reference voltage source, however, is a complex circuit that provides only a roughly constant voltage over changes in PVT.
A further drawback of switching converter 100 is that the converter requires a PID, which is also a complex circuit, to compensate for the second order effects of the LC network. Thus, there is a need for a DC-to-DC switching converter that provides a substantially constant supply voltage over changes in PVT without a band gap reference voltage source and a PID.